The Most Important Prior Art for Taiwan Semiconductor Teams Isn’t in the Claims. It’s in the Drawings.

Introduction

Consider the position of an IP team at a fabless chip design company in Hsinchu. They have designed a new integrated circuit — a power management IC with a novel gate driver topology. Before filing at TIPO, they need a prior art search. Before the product ships to TSMC, they need FTO clearance. Both searches begin the same way: enter the key technical features into a patent search tool and see what comes back.

What the text-based search will find: patents whose claim language or abstract text uses terms like “gate driver,” “power management IC,” or “topology.” What it will not find: the 2018 JPO filing by a Renesas predecessor company, the figure of which shows the identical circuit topology in the drain-gate coupling schematic — described in the patent claims in entirely different terminology. That patent is the blocking reference. The text search missed it.

Why Semiconductor Patent Disclosures Are Figure-Heavy

• Patent disclosure conventions in the semiconductor industry differ from most other technical domains in a specific way: the most technically precise description of an invention is often in the figures, not in the claims. Circuit topologies are inherently visual — the spatial arrangement of transistors, capacitors, and interconnects that constitutes the inventive concept cannot be fully described in claim text without becoming extraordinarily verbose. Device cross-sections — showing the layer structure of a CMOS gate or a fin field-effect transistor — convey structural information that claim language can approximate but not fully represent.
• JPO and KIPO applicants in particular have well-established conventions for figure-heavy patent disclosure. A Japanese semiconductor patent specification may contain 60 or more figures — each one a technical drawing that carries as much or more disclosure value as the claim text that nominally defines the protection scope. An FTO clearance search that reads only claim language from these specifications is reading less than half of the technical disclosure.

A Typical Taiwan Semiconductor FTO Scenario

The FTO workflow for a Taiwan-based semiconductor company going to market typically covers four jurisdictions: TIPO for Taiwan distribution, JPO for Japan market entry, KIPO for Korea (where component suppliers and OEM customers are), and USPTO for the US end market. A product that ships globally may also require EPO coverage for European automotive or industrial customers.

At each of these offices, the relevant prior art and active patents include filings by Japanese, Korean, US, and European companies — in four languages, with varying figure conventions, across 20 years of semiconductor technology development. A text-based FTO search covers the claim language in each jurisdiction. A complete FTO search covers both the claim language and the technical figures — because the blocking reference that terminates a market entry plan may be expressed in a circuit schematic, not a claim paragraph.

Figure 1: Text-only vs image-based FTO coverage for semiconductor patents — why text-based clearance has a structural blind spot for Taiwan semiconductor IP teams

The Supply Chain Complexity

The TSMC supply chain creates a specific FTO complexity that goes beyond the standard single-company clearance scenario. A chip shipped by a fabless designer to TSMC for fabrication, then to an OSAT for packaging, then to an OEM for system integration, passes through multiple patent exposure points before it reaches the end customer. Each entity in the supply chain has its own set of third-party patent risks — and an FTO clearance that covers only the fabless designer’s design may not address the exposure that arises from the fabrication process used by TSMC or the packaging technology used by the OSAT.

For Taiwan semiconductor IP teams managing FTO across this supply chain structure, the scope of the clearance analysis has to extend to process patents held by international competitors — many of which are expressed in detailed process flow figures, not just claim language. A text-only FTO search does not reach this class of prior patent art.

Figure 2: Taiwan semiconductor FTO clearance — the four jurisdictions required for global product launch and why unified multi-jurisdictional search is essential

What Image-Based FTO Search Actually Delivers

XLSCOUT’s Para-Picx technology adds image-based patent search to the FTO workflow. Upload a circuit schematic, a device cross-section, or a process flow diagram and Para-Picx searches the patent figure database for visual similarity — finding patents that disclose the same circuit topology, device structure, or process architecture, regardless of the claim language used to describe them.

The FTO Module, which incorporates Smart Feature Extraction — automatically identifying the key technical features from existing product documentation — provides the starting point for the clearance analysis. Para-Picx then extends that analysis to the figure-based disclosure that text-only clearance misses.

For Taiwan semiconductor IP teams, the combined workflow covers:

• Claim text analysis across TIPO, JPO, KIPO, and USPTO in a single semantic search
• Figure-based similarity search across the same jurisdictions for circuit topology and device structure prior art
• Confidence-ranked results that prioritise the most technically proximate blocking candidates for attorney review
• Multi-language semantic matching that finds the Japanese JPO filing and the Korean KIPO filing that describe the same invention in different terminology

Why This Matters Now

Taiwan semiconductor companies are in an increasingly active IP enforcement environment. US litigation involving TSMC supply chain patents has increased. Japanese and Korean companies have become more systematic in licensing their semiconductor IP to Taiwan-based customers. The FTO clearance that was adequate five years ago, when the enforcement environment was less active, may not be adequate today.

The gap between text-only FTO clearance and text-plus-image FTO clearance is not a theoretical quality difference. It is the difference between catching the blocking reference before the product ships and encountering it after the product is in market. For semiconductor products with design cycles measured in years, that timing difference is commercially significant.

XLSCOUT FTO Module + Para-Picx delivers unified text and image-based FTO clearance across TIPO, JPO, KIPO, and USPTO in a single workflow — designed for Taiwan semiconductor IP teams managing TSMC supply chain exposure.